Silicon Design Engineering Sr Manager
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Altera
Bayan Lepas
Lead the global PCIe/CXL Center of Excellent (CoE) team on developing latest state of the art PCIe/CXL solution for next generation FPGA in the latest process technology node. Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards to ensure key factors such as power, performance, area, and cost are... |
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6 days ago
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